1. Field of the Invention
The present invention relates to a regulator circuit. More particularly, the present invention relates to a regulator circuit for non-volatile memory.
2. Description of Related Art
The data stored in an Electrically Erasable Programmable Read-Only Memory (EEPROM) is retained even when the power is removed. The EEPROM can be directly written or erased with electronic signals if a user wants to write or erase the content stored in the EEPROM. For example, with a regulator of an internal voltage generating device, a plurality of stable and constant reference voltages are provided based on an output voltage of the boost circuit of the regulator, and the reference voltages are inputted to the EEPROM for writing or erasing data.
FIG. 1 is a circuit diagram of a positive voltage regulator described in the patent specification “Semiconductor Device with a Voltage Regulator” of U.S. Pat. No. 6,600,692 B2. Referring to FIG. 1, the positive voltage regulator 23 includes a driver 1 and a voltage-dividing circuit 2. Wherein, the driver 1 has transistors QP2 and QN2 coupled in series to an output node N0 connected to the internal voltage generating circuit, and the driver 1 outputs a regulating voltage Vreg at the output node N0. There are a pull-up current Iup through the transistor QP2 and a pull-down current Idn through the transistor QN2. Besides, the gates of the transistors QP2 and QP1 are coupled with each other to form a current mirror, and the sources of the transistors QP2 and QP1 are coupled to a boost voltage output node 80 to receive a boost voltage Vpp. The drain of the transistor QP1 is coupled to the drain of the transistor QN1, and the sources of the transistors QN1 and QN2 are both grounded voltage Vss.
The positive voltage regulator 23 further includes operational amplifiers OP1 and OP2. Wherein, the reversed-phase input terminal of the operational amplifier OP1 and the normal-phase input terminal of the operational amplifier OP2 are coupled to the reference voltage generating device 22. The reference voltage generating device 22 provides a reference voltage Vref1 to the reversed-phase input terminal of the operational amplifier OP1 and a reference voltage Vref2 to the normal-phase input terminal of the operational amplifier OP2. Wherein, the reference voltage Vref1 is greater than the reference voltage Vref2. In addition, the operational amplifiers OP1 and OP2 also receive a regulator enabling signal REGE. The output terminal of the operational amplifier OP1 is coupled to the gate of the transistor QN2, and meanwhile, the output terminal of the operational amplifier OP2 is coupled to the gate of the transistor QN1.
On the other hand, the voltage-dividing circuit 2 has resistors R1, R2, and R3 and transistors QN3 and QN4. Wherein, the resistors R1 and R2 are connected in series to node N1. The gate of the transistor QN3 is coupled to a verify-read control signal VRFY, the source thereof is coupled to the ground voltage Vss, and the drain thereof is coupled to node N3. Meanwhile, the gate of the transistor QN4 is coupled to a write control signal PROG, and the drain thereof is coupled to node N2. The voltage-dividing circuit 2 divides the regulating voltage Vreg and inputs the voltage on node N1 to the normal-phase input terminal of the operational amplifier OP1 and the reversed-phase input terminal of the operational amplifier OP2, so that the regulating voltage Vreg is feedbacked to driver 1 for maintaining the quantity of the regulating voltage Vreg.
FIG. 2 is a circuit diagram of a negative voltage regulator described in the patent specification “Semiconductor Device with a Negative Voltage Regulator” of U.S. Pat. No. 6,888,340 B1. Referring to FIG. 2, the semiconductor device 200 has a negative voltage regulator 20, which includes a voltage regulator 210, a current source circuit 220, a reference voltage generator 230, a voltage divider 240, a driver 250, and operational amplifiers 261 and 262. Wherein, the voltage regulator 210 regulates a voltage source VDD, and the voltage regulator 210 has a transistor p3 and an operational amplifier 263. The drain of the transistor p3 and the normal-phase input terminal of the operational amplifier 263 are both coupled to node Ns. In addition, the reference voltage generator 230 generates and outputs a reference voltage Vref 21 to the reversed-phase input terminal of the operational amplifier 263 and a reference voltage Vref 22 to the reversed-phase input terminal of the operational amplifier 261 and the normal-phase input terminal of the operational amplifier 262.
The current source circuit 220 has the transistors n1 and n2. The sources of the transistors n1 and n2 are both coupled to node NIN, and a negative input voltage VIN2 is inputted to the negative voltage regulator 20 at node NIN. Besides, the voltage divider 240 has resistors R21 and R22, wherein one terminal of the resistors R21 and one terminal of the resistor R22 are both coupled to node NFEBK3, and node NFEBK3 is electrically coupled to the normal-phase input terminal of the operational amplifier 261 and the reversed-phase input terminal of the operational amplifier 262. The other terminal of the resistor R21 is coupled to the normal-phase input terminal of the operational amplifier 263, and the other terminal of the resistor R22 is coupled to node NOUT, which carries a negative output voltage VOUT2.
Moreover, the driver 250 has transistors p1 and p2, wherein the gates of the transistors p1 and p2 are respectively coupled to the output terminal of the operational amplifier 261 and the output terminal of the operational amplifier 262.
It can be understood from FIG. 1 that the level of the regulating voltage Vreg is easily affected by the outputs of the operational amplifiers OP1 and OP2. In other words, the quantity of the regulating voltage Vreg is limited by the output level of the operational amplifiers OP1 and OP2. Similarly, in FIG. 2, the quantity of the negative output voltage VOUT2 is also limited by the output level of the operational amplifiers 261 and 262. Thus, the range of the output voltage of a conventional circuit is limited.